1. Field of the Invention
The present invention relates to an integrated level shifting latch circuit, and to a method of operation of such a latch circuit.
2. Description of the Prior Art
A level shifter circuit is used when there is a need to pass signals from one voltage domain to a different voltage domain. In modern data processing systems, it is becoming more and more common for certain parts of the data processing system to operate in a different voltage domain to one or more other parts. For example, a trend within integrated circuits is the increasingly common use of embedded memory, such as SRAM memory. With the reduction in size of process geometries, the individual memory cells within the memory are becoming less stable. To reduce the power consumption of the integrated circuit, it is desirable to reduce the operating voltage of the components within the integrated circuit. However, whilst this can be done for many of the components within the integrated circuit, including access logic circuitry associated with the memory device, it is often the case that a higher voltage is needed to drive the array of memory cells within the memory device in order to enhance the stability of those cells. Hence, embedded SRAM bit cells may use a higher voltage supply to guarantee state retention, whilst the rest of the system, including the access logic circuitry employed to access those bit cells within the memory device, may use a lower voltage supply to reduce power consumption. In order to maintain performance, and reduce switching power, level shifters are provided to pass signals between these domains.
Often, the signals generated in the lower voltage domain need to be latched before processing within the higher voltage domain. Hence, considering the example of a memory device, the various signals generated by the access logic circuitry in the lower voltage domain will often be latched using latch circuitry before further processing within the higher voltage domain containing the array of bit cells. It is common practice to first level shift such signals on the periphery of the lower voltage domain to the higher voltage domain, and then latch those signals in the higher voltage domain.
U.S. Pat. No. 4,978,870 describes a technique that uses a traditional level shifter followed by a separate latch circuit to enable input signals to be level shifted and then subsequently latched. One problem with such an approach is that the circuitry has a relatively large area and power consumption, due to the presence of the separate level shifter circuitry and subsequent latch circuitry. It would also be desirable to provide a higher performance solution.
U.S. Pat. No. 6,351,173 describes an integrated level shifting latch for an input/output section of an integrated circuit. With the circuit described in this patent, the voltage shifting range possible using the circuit depends on the sizing ratio of the NMOS and PMOS components within the design. As the extent of level shifting required increases, the latency involved in the shifting operation will increase and ultimately could result in failure of the circuitry. This is becoming more and more significant in modern data processing systems, where the difference in voltage between the lower voltage domain and the higher voltage domain can be as large as 400 mV when taking into account power supply tolerance variation and IR drop.
US 2012/0044009 A1 describes a level-shifting latch circuit. However, in the implementation described the latch is not clocked, and hence does not provide a true synchronous latch, as will be required in many implementations, such as at the interface between the access logic circuitry and the array of bit cells within a memory device. Also, the input is not gated by the clock, so any change in the input can impact on the “latched” state.
Commonly owned co-pending patent application US 2008/0157848 A1, the entire contents of which are hereby incorporated by reference, describes a level shifting circuit for use between voltage domains, which is able to operate efficiently for a large range of voltage difference between the lower voltage domain and the higher voltage domain. However, a separate latch circuit would need to be provided following such a level shifter circuit in order to perform the earlier mentioned level shifting and latch functionality.
It would be desirable to provide an integrated level shifting latch circuit which has improved performance, and is more area and power efficient, than providing a level shifting circuit followed by a separate latch circuit, but which can also accommodate an increased variation in voltage between the lower voltage domain and the higher voltage domain than known integrated solutions.